Digital vector generator



May 5, 1970 1-. T. CALLAHAN ETAL v3,510,365

- A 1 DIGITAL VECTOR GENERATOR I Filed Jan. 21. 1969 I 3 sheetssheet 2COMPOSITE PULSE TRAIN GATE 2 I GATE 2' GATING GATE 2 LEVELS GATE 2 FROMGATE 2 AXGIAY n REGIsTERs GATE 2 O l 2 3 4 2 PULSES 2 PULSES ZPULSESZPULSES 2 PULSES Z PULSES PULSE GROUPS FROM CLOCK PULSE GENERATOR 4FIG.3A IIIIIII|II'IIIIII 3 I PULSE 2 I l I I I I l GROUP SPACING 22 I II I T IME FOR ONE CYCLE OF CLOCK PULSES 38 REGISTER ALL PULSE GROUPSGATEDTHR'U IIIIIlIIIIIIIIIIIIIIIIIIIIIIIIII RATE MULTIPLIER FIG.3C

ZAZZMIPULSE I II III III III III III III I GROUPS GATEG THRU RATEMULTIPLIER INVENTOR. ALLEN J. woRTERs BY DOMENIC A.ZAMBUTO THOMAS T.CALLAHAN 8W4 yAGENT May 5,1?10 'r.'r. GALLAHAN ERTAL I "3,510,865

DIGITAL VECTOR GENERATOR Filed Jan; 21, 1969 s Sheds-Sheet 3 TO RATEMULTIPLIERS FROM 1 AX ANDAY REGISTERS Fl. IF-FLOP F .lP-FLOP FLIP-FLOPFLIP-FLOP a o o o Q R iao la! 52 163 I v c 6 0' 6 FROM R R R ROSCILLATOR RFSET 42 FROM TIME REGISTER 4! FIG. 4

PULSE GROUP 2, FL I 1 F1 FL F1 PULSE GROUP 2 1 TI PULSE GROUP 2 Fl PULSEGROUP 2' v L INVENTORS ALLEN J. WORTERS BY DOMENLC 'A.ZAMBUTO THOMASTICALLAHAN al- J 1 4 fl y AGENT United States Patent US. Cl. 340-324 9Claims ABSTRACT on THE DISCLOSURE A digital vector generator employing asource of digital signals representing the starting point, direction andlength of the vector to be displayed on a cathode ray tube (CRT).Digital logic converts the direction and length signals into pulsetrains having varying time scales and varying numbers of pulses, both ofwhich are. substantially proportional to the vector length. The pulsetrain is combined with the starting point signals and converted to ananalog signal for display on the CRT.

CROSS-REFERENCE TO RELATED APPLICATION This application is acontinuation-in-part of copending application Ser. No. 593,193, filedNov. 9, 1966, now abandoned.

BACKGROUND OF THE INVENTION This invention is concemed with displaysystems and, in particular, with a system for digitally generatingvectors for display on such devices as cathode ray tubes (CRT).

Many dynamic display systems presently available for presentation ofgraphical, tactical or other data employ analog techniques, andif thedisplay system is to be linked to a digital computer or other processor,specific interface circuitry must be designed to suit the particularinstallation. These analog circuits, in addition to being rigid indesign, must be tailored to the speed, resolution or linearity requiredin particular instance. It wou d be advantageous to have, and it is anobject of this invention to provide, a simple and versatile displaysystem for operation with high speed digital processing equipment andwhich is easily adaptable to varying system parameters.

BRIEF DESCRIPTION OF THE INVENTION Briefly, a digital vector generatoraccording to the present invention comprises a digitally controlleddisplay system operative to generate and display vectors on a displaydevice such as a CRT. Digital information representing the startingpoint, magnitude and direction of a vector is provided by asuitablesource such as a digital computer. Connected to the computer isa pulse train generator which converts the digital informationrepresenting the vector magnitude from the computer into pulse trains inwhich the numbers of pulses and the time bases are both substantiallyproportional to the vector magnitude thus insuring that the writingspeed and intensity of the CRT will be constant for long and shortvectors. A summing means, for example, UP/ DOWN counters, adds thevector direction and magnitude information from the pulse traingenerator to the starting point information already stored in thesumming means. The digital output signal from the summing means isconverted to the necessary signal format for display.

BRIEF DESCRIPTION OF THE DRAWINGS This invention will be more fullydescribed in the following detailed description read in conjunction withthe accompanying drawings, wherein:

3,510,865 Patented May 5, 1970 FIG. 1 is a block diagram of the digitalvector generator system;

FIG. 2 is a block diagram of a digital rate multiplier useful in thesystem of FIG. 1;

FIGS. 3A, 3B and 3C are timing diagrams useful in explaining theoperation of the rate multiplier of FIG. 2;

FIG. 4 is a block diagram of a clock pulse register employed in thevector generator of FIG. 1; and

FIG. 5 is a time diagram useful in explaining the operation of the clockpulse register of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION The requirement of a vectorgenerator is to move a CRT beam from a vector starting point (X, Y) toits end point (X +AX, Y+AY). This requirement may be broken down intothree separate requirements:

(1) during the writing time of the vector, the X and Y components mustbe counted up (or down) by pulses equal in number to the binary value ofthe respective components;

(2) the pulses used to increment the X and Y components must be spreadevenly within the writing time of the CRT so that the vector will besmooth and so that the end point of the components will be reachedtogether; and

(3) the writing time of the vector should be substantially proportionalto the magnitude of the vector so that the writing speed will beconstant and the intensity equal for long and short vectors.

Referring to FIG. 1, a preferred embodiment of the present inventionwhich realizes these requirements comprises a display unit 10 includinga CRT 12, horizontal and vertical deflection amplifiers 14 and 16 anddigital to analog converters 18 and 20. To provide the vector startingpoint, direction and length, a source of digital signals, such as acomputer 22, is connected to X and Y summing means such as UP/DOWNcounters 24 and 26, respectively. A pulse train generator 11, to beexplained in detail hereinafter, has AX and AY inputs from the computer22 and AX and AY output connections to the respective UP/DOWN counters24 and 26.

In operation, digital information representing the starting point of avector to be displayed is supplied from the computer 22 as a referenceto the UP/DOWN counters 24 and 26, and information, AX and AY,indicative of direction and length of the vectors, is directed to thepulse train generator 11. For each component of the vector, the pulsetrain generator 11 converts the length information into a pulse trainwherein the number of pulses and time base of the pulse train areproportional to the length. Each pulse train is then directed to theappropriate UP/DOWN counter where it is combined with the starting pointinformation. The UP/ DOWN counters 24 and 26 accept the pulse trains andeither count up or down according to the sign in the AX and AY registers28 and 30. A digital output signal from each UP/ DOWN counter isdirected to the appropriate deflection plate of the CRT 12 via itsrespective D/A converter and deflection amplifier.

The pulse train generator 11 includes a pair of storage devices, forexample, AX and AY registers 28 and 30, having input connections fromthe computer 22. Gating means such as rate multipliers 34 and 36 havefirst input connections from the respective AX and AY registers 28 and30 and second input connections from a clock pulse generator 31, to bediscussed in detail hereinafter. The output connections from the ratemultipliers 34 and 36 are connected to the respective X and Y UP/ DOWNcounters 24 and 26. Also connected to the AX and AY registers 28 and 30and to the clock pulse generator 31 is an output connection from controllogic 32, also to be discussed in detail hereinafter.

As stated hereinabove, the information representing the starting pointof the vector is supplied from the computer 22 to the X and Y UP/DOWNcounters 24 and 26, and the information indicative of direction andlength, AX and AY, of the vectors are applied to the AX and AY registers28 and 30. Control logic 32 strobes the data from the computer intoregisters 28 and 30 where it becomes available to respective ratemultipliers 34 and 36 which are operative to generate pulse trainsrepresenting the binary numbr in the registers 28 and 30. These pulsetrains are transferred to respective UP/DOWN counters 24 and 26 wherethe starting point information is stored.

The rate multiplier is shown in greater detail in FIG. 2 and includes aplurality of AND gates 40 whose outputs are connected to correspondinginputs of an OR gate 142. The input from the clock pulse generator 31provides pulse groups where the number of pulses on each line are ofincreasing binary significance, i.e., 1, 2, 4, 8 Each pulse group isapplied to a corresponding input line of the several gates 40 and in thetime sequence shown in FIG. 3A. The second set of input lines to gates40 provide gating levels from respective AX and AY registers to controlwhich of the pulse groups are allowed to pass through their respectiveAND gates 40 to the OR gate 142. The output of the OR gate is then acomposite pulse train representing the magnitude of the storedcomponent.

FIG. 3B shows a composite train that would appear at the output of ORgate 142 if the vector in the AX register 28 were of the maximummagnitude; that is, all the pulse groups were gated through the ANDgates 40. FIG. 3C shows a composite pulse train that results if pulsegroups 2 2 and 2 are passed through their respective AND gates 40 bygate pulses occurring at the corresponding gating inputs. The pulsegroups which are passed are then combined in OR gate 142 to form thecomposite pulse train representing the magnitude of the component.

To provide a smooth vector display on the CRT, the pulse grouprepresenting each component must be evenly spread throughout the writingperiod or illustrated, for example, in FIGS. 3B and 3C. This even pulsespread is accomplished by means of the clock pulse generator 31 which isoperative to gate the pulse groups out in the time sequence shown inFIG. 3A. It can be seen that no two pulses occur at the same time andthat the number of pulses comprising each binary level 2 2 etc., arespread evenly over one clock period. By arranging the pulses such thatno pulses in one pulse group occur at the same time as a pulse inanother pulse group, the pulse groups may be added to form a pulse trainwithout an overlap of any pulses. By spreading the number of pulses ineach pulse group evenly over the time'for one cycle, any combination ofpulse groups will produce a vector display spread evenly in time.

The clock pulse generator 31 includes an oscillator 42- connected to aclock pulse register 38. Also connected to the clock pulse register 38are input connections from the respective AX and AY registers 28 and 30and a time register 41 such as a well-known ripple counter which, inturn, has an input connection from the control logic 32. One embodimentof the clock pulse register 38, shown in FIG. 4, is a binary counterincluding a plurality of fiipflops, four of which are shown forillustration purposes, 160-163, each having first and second outputconnections and an input connection. Associated with each flop-flop160-163 is a respective AND gate 200-203. Each AND gate 200-203 hasinput connections from a gate 150, the first output connection of itsassociated flip-flop and the second output connections of all thepreceding flip-flops in the chain. The trigger input connection, C foreach of the flip-flops 161-163, is connected to the first outputconnection of the preceding flip-flop in the chain. The gate 150 hasinput connections from the oscillator 42, the AX and AY registers andthe time register 41, and output connections to each AND gate 200-203and the trigger input terminal C of flip-flop 160.

The timing diagram of FIG. 5 may be employed in conjunction with FIG. 4to understand the operation of the clock pulse register 38. As indicatedin the timing diagram, with every input pulse from the oscillator 42passed through gate 150, the binary counter including the flip-flops160-163 is incremented to the next binary state. For example, the ANDgate 200, associated with the lowest ordered flip-fiop 160, passes theinput count pulse from the oscillator 42 whenever its associatedflip-flop 160 is reset thus producing the pulse group 2 The next ANDgate 201, associated with the next higher flip-flop 160, passes theinput count from the oscillator 42 when the flip-flop 161 is reset andthe lower order flipflop 160 is set. The result is a second pulse group2 appearing at the output terminal of gate 201 and having a frequency ofhalf the previous one, 2 offset by one oscillator pulse. As shown inFIG. 5, the same pattern continues for each flip-flop and gate in theclock pulse register 38. The input pulses from the oscillator 42 arepassed when the flip-flop associated with an AND gate is reset and allprevious lower order flip-flops are set. This results in each successivepulse group being half the frequency of the previous one and offset byone count from the previous group thus yielding the desired input signalto the rate multipliers 34 and 36, as shown in FIG. 3A.

The gate has two enabling signals, both of which are necessary to passthe oscillator signal and thereby activate the clock pulse register 38.One enabling signal indicates the end of the normalizing operation, tobe explained in detail hereinafter, and may originate from the mostsignificant bit positions of the AX and AY registers 28 and 30. A binaryONE shifted into the most significant bit position of either of the AXand AY registers 28 or 30 will produce the enabling signal. The secondsignal originates in the time register 41 and is removed when the timeregister count reaches zero. The time register 41 is a simple counterhaving a preset stored number from which it counts down to zero. Thenumber stored in the time register 41 is related to the maximum numberof pulses required from the clock register 38. Thus, the clock pulseregister 38 is enabled from the end of the normalizing cycle to theinstant the time register 41 is counted down to zero.

The system described thus far would succeed in drawing vectors or lineson the CRT 12 by loading the starting point information in the UP/ DOWNcounters 24 and 26, loading the magnitude and direction data into the AXand AY registers 28 and 30, and the enabling the clock pulse register 38to produce the requisite pulse groups. The appropriate pulse groups aredirected to X and Y UP/ DOWN counters 24 and 26 by the respective ratemultipliers 34 and 36. The operation described thus far would result inall vectors being written on the CRT 12 in the same length of timeresulting in the writing rate on the CRT to vary over a range that maybe larger than 1000: 1.

To write all vectors in a time which is substantially proportional tothe length of the vector, normalization is introduced before the clockpulse register 38 is enabled. Normalization is accomplished by shiftingthe data in the AX and AY registers 34 and 36 one bit at a time towardsthe most significant bit position in each register. If no other actionwere taken, with each shift of the AX and AY registers 28 and 30 twiceas many pulses would appear in the composite pulse trains appearing atthe output of the rate multipliers 34 and 36 as would normally occur fora vector of a given magnitude. However, part of the normalization is toshift the value in the time register 41 one bit towards the leastsignificant binary position which results in the clock register 38 beingenabled for one half the time. Given a fixed frequency of operation asset by oscillator 42, the time to count a number, n/Z, down to zero ishalf the time required to count a number, n, down to zero. Since theclock pulse register 38 is only activated during the period of time thatthe time register 4 is counting down to zero, with each shift pulseduring normalization the time that the clock pulse register 38 isactivated will be cut in half. By shifting the time register 41concurrent with shifting the AX and AY registers, the same number ofpulses appear in the composite pulse trains, but the period of time ishalved with each shift. This normalization is repeated until a ONE isdetected in the highest order bit position of either the AX register 28or the AY register 30.

Normalization does not change the number of pulses in the compositepulse trains. It does change the length of time in which these pulsesoccur. If T is the maximum length of time required to draw the longestline, then the time utilized to draw any line is T/m' where m is thenumber of shift pulses during normalization. If the longest line is kTwhere k is a simple proportionality constant,

then it would be desirable for the length of the line drawn in time T/mlto be kT/m Normalization does not produce this result exactly butinstead draws lines in time T/m which vary from .SkT/m to /2IcT/m. Thevariation, 2.8: l, is a significant improvement over the 1000z1 rangepresent before normalization and may be said to represent a substantialproportionality between line length and the line writing time.

One embodiment of the control logic 32 which may be employed toaccomplish the required shifting for normalization is shown in FIG. 1and includes a strobe 50 having a first output connection to thecomputer 22 and a second output connection to a first flip-flop 52. Afirst gate 56 has an input connection from the first flip-flop 52 andinput connections from the AX and AY registers 28 and 30. A secondflip-flop 58 has an input connection from the first gate 56 and anoutput connection to a second gate 60. A second input connection to thesecond gate 60 comes from a clock.

In operation, the signal from the strobe 50 is sent to the computer 22to load the UP/DOWN counters 24 and 26 and the AX and AY registers 28and 30. After the data is received, the strobe sends a signal to thefirst flip-flop 52 which, in turn, supplies an input signal to the firstgate 56. The other two inputs to the first gate 56 originate at the ONEoutput of the most significant bit position in the AX and AY registers28 and 30. If neither the AX register 28 or the AY register 30 have aONE in the most significant bit position, the clock pulses are passedthrough the second gate 60 to the AX and AY registers 28 and 30 and thetime register 41 as a series of shift pulses to normalize the data asexplained hereinabove. When a ONE appears in the most significant bitposition of either the AX orAY registers 28 or 30, it passes through thefirst gate 56 and resets flip-flop 58 which, in turn, inhibits thesecond gate 60 blocking the clock signal and thus stopping the shiftpulses to the time register 41 and the AX and AY registers 28 and 30.When normalization is thus ended, the pulses from oscillator 42 arepassed to the clock pulse register 38 to produce the pulse groups and tothe time register 41 counting it down towards zero. For as long as thetime register is still nonzero, the pulse groups are produced, combinedinto composite trains, and used to count up or down the startingpoistion values in the AX and AY registers 28 and 30, thus describingthe line as it moves from its original position (X, Y) to its finalposition (X+AX, Y+AY).

From the foregoing, it is evident that a digital vector display systemhas been provided which is simple in construction and extremelyflexible. The system is adaptable to larger or smaller displays bymerely adding to or subtracting from the length of the variousregisters, and it may be made faster or slower merely by changing thefrequency of the clock.

What is claimed is:

1. A digital vector generator comprising:

a source of digital signals representing the starting point, directionand length of a vector to be displayed;

means for generating pulse trains in response to the digital signalsrepresenting the length of the components of the vector from said sourceof digital signals, each of said pulse trains having a number of pulsesproportional to the length of the component and having a time base, saidnumber of pulses being substantially evenly distributed within said timebase;

summing means having input connections from said source of digitalsignals and from said means for generating pulse trains and beingoperative in response to the digital signal representing the startingpoint from said source of digital signals and to the pulse trains fromsaid means for generating pulse trains to generate a composite digitalsignal, representing the vector; and

display means connected to said summing means and being operative inresponse to the composite digital signal from said summing means todisplay said vector.

2. A digital vector generator according to claim 1 wherein said meansfor generating pulse trains includes: first storage means having a mostsignificant bit position and being operative to store the digitalsignals representing the direction and length of a first of the vectorcomponents from said source of digital signals;

a clock pulse generator having a plurality of output terminals and beingoperable to generate pulse groups, each pulse group being of increasingbinary significance and each group being uniformly spaced in time; and

first gating means having input connections from said first storagemeans and said clock pulse generator and being operative in response tothe signals from said first storage means and said clock pulse generatorto generate a pulse train in which the number of pulses is proportionalto the length of said first vector component.

3. A digital vector generator according to claim 2 wherein said clockpulse generator includes:

an oscillator operative to generate a series of pulses at a fixed rate;

counting means operative to count down to zero from a predeterminedreference number stored in said counting means and to generate a controlsignal when the count reaches zero; and

clock pulse register means having input connections from saidoscillator, said counting means and said first storage means, and aplurality of output connections to said first gating means, said clockpulse register means being operative in response to the pulses from saidoscillator to generate a plurality of pulse groups, each pulse groupoccurring on one of the plurality of output connections and being ofincreasing binary significance and uniformly distributed over apredetermined time interval such that no two pulses of said plurality ofpulses occur simultaneously, said clock pulse register means beingoperative to generate said pulse groups when a predetermined signal isreceived from said first storage means and in the absence of the controlsignal from said counting means.

4. A digital vector generator according to claim 3 wherein said clockregister means includes:

second gating means having input connections from said first storagemeans, said oscillator and said counting means, said second gating meansbeing operative to pass the output signal from said oscillator when asignal is received from said first storage means and to inhibit theoscillator signal when a control signal is received from said countingmeans;

a plurality of serially connected flip-flops, each having an inputconnection and first and second output connections, said first outputconnection being connected to the input connection of the precedingflip-flop, the first of said plurality of flip-flops having its inputconnection connected to the second gating means; and

a first plurality of AND gates, each of which is associated with one ofsaid plurality of serially connected flip-flops and each of which hasinput connections from the second gating means, the second outputconnection of its associated flip-flop and the first output connectionof each preceding flip-flop, each of said AND gates being operative topass the output signal from said second gating means upon coincidence ofsignals at its input connections.

5. A digital vector generator according to claim 2 wherein said firststorage means is a shift register having a plurality of stages andwherein said first gating means includes:

a second plurality of AND gates, each having a first input connectionfrom one of the stages of said first storage means and a second inputconnection from one of the plurality of output terminals of said clockpulse generator, each of said AND gates being operable to pass itsIespective pulse group from said clock pulse generator when a ONE isstored in its respective stage of said shift register; and

an OR gate having input connections from each of said second pluralityof AND gates and being operative to pass all pulse groups appearing atits input connection whereby a composite digital pulse trainrepresenting the length of the first component of the vector isgenerated.

6. A digital vector generator according to claim 2 wherein said meansfor generating pulse trains further includes normalizing means connectedto said first storage means and to said clock pulse generator foradjusting the time base of said pulse trains to be substantiallyproportional to the length of the vector component.

7. A digital vector generator according to claim 6 wherein saidnormalizing means includes:

logic means having an input connection from said first storage means, afirst output connection to said first storage means and a second outputconnection to said clock pulse generator, said logic means beingoperable to supply a series of shift pulses to said first storage meansand to said clock pulse generator, said first storage means beingoperative in response to the shift pulses from said logic means to shiftthe digital information towards the most significant bit position andsaid clock pulse generator being operative in response to each shiftpulse from said logic means to half the time of each output pulse groupwhereby the number of pulses in each of said pulse groups is constantfor a given vector component length.

8. A digital vector generator according to claim 7 wherein said logicmeans includes:

a clock operative to generate a series of shift pulses;

third gating means having an input connection to said clock and anoutput connection to said first storage means and to said clock pulsegenerator, said third gating means being operative to pass the shiftpulses from said clock to said clock pulse generator and to said firststorage means; and

inhibiting means having an input connection from said first storagemeans and being operative in response to digital information in the mostsignificant bit position of said first storage means to inhibit thethird gating means.

9. A digital vector generator according to claim 1 wherein said summingmeans includes UP/ DOWN countters operative to store the starting pointinformation of the vector to be displayed, said UP/ DOWN counters beingoperative to add the pulse trains from said means for generating pulsetrains to the starting point information to form a composite digitalsignal representing the vector to be displayed.

References Cited UNITED STATES PATENTS 3,018,045 1/1962 Poland 235150.533,205,344 9/1965 Taylor et al. 340324.1 3,238,462 3/1966 Ballard et al.32872 3,404,394 10/1968 Bassett 340324.1 3,422,304 1/1969 Thorpe 31518JOHN W. CALDWELL, Primary Examiner M. M. CURTIS, Assistant Examiner US.Cl. X.R. 3l5-18

